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A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

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Abstract

Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1 GHz with a performance suitable for cellular standards. It shows a phase noise floor below −150 dBc/Hz and a spurious level below −35 dBc. The multiplier by 3/2 consumes 5 mA and the VCO draws 10 mA from a 1.2 V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this solution, compared to the use of multiple LC VCOs.

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Notes

  1. It is worth noticing that it is not desirable to let the VCO operate at the carrier frequency, to avoid pulling from the power amplifier of the radio.

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Acknowledgments

This work has been partially supported by the VINNOVA Industrial Excellence Center in System Design on Silicon (SoS) at the Dept. of Electrical and Information Technology, Lund University, Sweden.

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Authors and Affiliations

  1. Dipartimento di Ingegneria dell’Informazione, Università di Padova, 35131, Padova, Italy

    Andrea Bevilacqua

  2. Department of Electrical and Information Technology, Lund University, 221 00, Lund, Sweden

    Pietro Andreani

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  1. Andrea Bevilacqua
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  2. Pietro Andreani
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Correspondence to Andrea Bevilacqua.

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Bevilacqua, A., Andreani, P. A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2. Analog Integr Circ Sig Process 74, 11–20 (2013). https://doi.org/10.1007/s10470-012-9892-x

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  • DOI: https://doi.org/10.1007/s10470-012-9892-x

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